__Design of a single-state Audio-frequency Amplifer__

In the design of a single-stage audio-frequency amplifier a number of factors must be taken into account. These include the choice of operating point and the required voltage gain. Other factors such as the required bandwidth and the noise performance are also of importance but are beyond the scope of this book. There are several different approaches to the design of an amplifier available and here just one of them is given.

Suppose that an amplifier stage is to deliver the maximum possible output voltage so that the d.c. collector-emitter voltage *V _{CE}* will be set at one-half of the supply voltage

*V*. Assuming for the moment, that the rest of the supply voltage is dropped across the collector

_{CC}resistor *R _{3}*, then

*V*/2 =

_{cc}*l*). This gives the maximum possible output voltage. The voltage gain

_{c}R_{3}*Av*= g

*= 40*

_{m}R_{3}*l*X

_{c}*V*/2

_{cc}*l*

_{c}_{ }= 20

*V*. This approximate relationship will allow a choice to be made of the collector supply voltage to allow a wanted gain to be obtained, or alternatively, if the supply voltage is already fixed by other considerations, it will establish the maximum possible voltage gain.

_{cc}A suitable d.c. load line can be drawn on the output characteristics of the transistor and the operating point located at *V _{cc}*/2 volts. This allows the collector current to be detennined. Alternatively, a collector current may be arbitrarily selected, which will very often be the value quoted in the data sheet for the typical value of

*h*.

_{FE}The collector resistor can then be determined from *R _{3}* =

*V*2

_{cc}/*I*

*. The potential divider bias circuit must establish the required operating point and also provide adequate d.c. stability. If*

_{c}*h*

_{FE}R_{4}>>

*R*/(

_{1}R_{2}*R*) the collector current will be very nearly equal to (

_{1}+ R_{2}*V*)

_{B}- V_{BE}*IR*

_{4}, i.e. it will be independent of

*h*. The collector current is then still subject to variations due to changes in V

_{FE}_{SE}but this factor may be minimized by making

*V*several times larger than

_{B}*V*Since

_{BE}*V*this means that the voltage across

_{E}= V_{E}+ V_{BE}*R*should not be less than about 1

_{4}*V*. A good rule is to make

*V*equal to

_{E}*V*/10 with a minimum value of I V.

_{cc}For the circuit to operate correctly the base voltage *V _{B}* should remain more or less constant at

*V*as the collector current and thus

_{B}= VccR_{2}/(R_{1}+ R_{2})*V*=

_{E}*I*varies. To achieve this the current flowing through the lower bias resistor

_{c}R_{4}*R*must be several times larger, by a factor n, than the base current

_{2}*I*=

_{B}*Ic/h*. The larger the factor n the better will be the d.c. stability of the circuit but the lower will be the values of the resistors

_{FE}*R*and

_{1}*R*. Since R

_{2}*1*and R

*2*are effectively in parallel, both with the signal path and with one another, their values must not be too small. This means that the choice of n must be a compromise between the a.c. and d.c. performances of the circuit. A suitable choice for

*n*is 10.

Then, *R _{2} = V_{B}/nI_{B}* and

*R*. Calculation of suitable values for the coupling and decoupling capacitors is more difficult and values such as those quoted in Table 1 should be used.

_{1}= (Vcc – V_{B})/(n+ I)I_{B}__Example 14 __

Design an audio-frequency single-stage amplifier to have a voltage gain of about 240 using the transistor whose characteristics are given in Fig. 36. The maximum possible output voltage is required.

__Solution__

Voltage gain = 240 = 20*V** _{cc }*, or

*V*

*= 240/20 = 12 V. The operating point is then set at*

_{cc}*V*= 6 V,

_{CE}*I*= 15 /

_{B}*πA*. The d.c. load line has been drawn through these two points. The d.c. collector current is then 1.5 mA and

*h*

_{FE}= (1.5 x 10

^{-3})/(15 x 10

^{-6}) = 100.

The slope of the load line is (12 - 6)/(1.5 - 0) x 10^{-3} = 4000 Ω. The emitter voltage *V _{E}* =

*Vcc*/l0 = 12/10 = 1.2 V. Hence,

*R*= 1.2/(1.5 X

_{4}10^{-3}) = 800 Ω. Choosing the nearest preferred values for *R _{3}* and

*R*;

_{4}*R*= 3900 Ω and OO

_{3}*R*= 820 Ω. Now the voltage drop across (

_{4}*R*) is 1.5 X 10

_{3}+ R_{4}^{-3}X (3900 + 820) = 7 V which leaves

*V*. as 5 V.

_{CE}The base current *I _{B}* =

*I*/

_{c}*h*= 15 πA. Therefore, choose the current in

_{FE}*R*to be 150 μA. From Fig. 36a , when

_{2 }*I*= 15 μA,

_{B}*V*

_{BE}_{ }= 0.65 V, giving

*Vs*= 1.2 + 0.65 = 1.85 V. Then,

*R _{2}* = 1.85/(10 x 15 x 10

^{-6}) = 12.3 kΩ

*R _{1}* = (12 - 1.85)/(11 x 15 x 10

^{-6}) = 61.5 kΩ

Choosing the nearest preferred values*, R _{2}* = 12 kΩ and

*R*= 62 kΩ.

_{1}The midband voltage gain will be g* _{m}R_{3}* = 38 x 1.5 x 10

^{-3}x 3900 = 222. To increase the gain nearer to the wanted target of 240 the next higher preferred value for

*R*could be used. i.e.

_{3}*R*= 4300 Ω . Then

_{3}*A*= 245 but the maximum output voltage will be reduced .

_{v}