__Multi-stage Amplifiers__

__Multi-stage Amplifiers__

Very often the voltage gain that an amplifier is required to provide is greater than can be supplied by a single stage. It is then necessary to connect two, or more, stages in cascade to obtain the required gain The term 'cascade' means that the output terminals of one stage are connected to the input terminals of the next stage. The overall voltage gain of a number of cascaded amplifier stages is equal to the product of their individual gains, i.e. *G = G _{1} X G_{2} X G_{3}* …

*Example 15 *

*Example 15*

An amplifier stage has a voltage gain of *A _{v}* . If two such stages are connected in cascade to obtain an overall voltage gain of 1000, what is the required gain per stage?

__Solution __

*G _{1} X G_{2} = G^{2}* = 1000

^{3}√1000 = 31.62 (*Ans*.)

__Exercises__

__Exercises__

1 - Fig. 37 shows how the d.c. current gain *h _{FE}* of a transistor varies with the collector current

*I*

*. If the maximum gain is required determine the value of*

_{e}*I*

*that should be chosen.*

_{c}2 - List the factors that should be taken into account when choosing a suitable operating point for a transistor.

3- The mutual characteristic of an n-channel enhancement-mode MOSFET is shown in Fig. 38. The bias voltage is + 2 V. If a sinusoidal signal of peak value 1_{V} is applied to the device determine the waveform of the drain current.

4- Explain, with the aid of a typical mutual characteristic, why Class B or Class C bias cannot be used with a single-ended resistance-loaded amplifier.

5- Fig. 39 shows a typical mutual characteristic for a bipolar transistor. Determine suitable base-emitter bias voltages for (*a*) Class A, (*b*) Class 8 and (*c*) Class C bias.

6- Explain why d.c. stabilization of a FET is necessary even though thermal runaway is not a problem. Hence, explain the disadvantage of the circuit given by Fig. 40(*a*).

7- In Fig. 41(*a*), *V _{DD}* = 12 V.

*R*= 3 kΩ and

_{3}*V*= 6 V. Calculate the drain current. If

_{DS}*R*calculate

_{1}= R_{2}*V*also.

_{GS}8- In the circuit of Fig. 6.40(*b*). *R _{1}* = 470 kΩ,

*R*= 3 kΩ ,

_{3}*R*= 1.2 kΩ and

_{3}*V*= 12 V. Calculate the gate-source bias voltage if the drain current is 1.5mA.

_{DD}9- In Fig. 40(*c*), *R _{2}* = 150 kΩ.

*R*= 22 kΩ ,

_{1}*R*= 2 kΩ and

_{3}*R*= 3.8 kΩ.

_{4}If *V _{DD}*

_{ }= 15 V and

*I*= 1.5 mA calculate (

_{D}*a*)

*V*

_{D}*and (*

_{s}*b*)

*V*

_{G}*.*

_{s}10- In Fig. 41(*b*) R1 = 300 kΩ and *R _{l}* = 4.7 kΩ. if

*V*= 5 V, what is the value of

_{DS}*V*?

_{GS}11- In the circuit of Fig. 42. *V _{CC }*= 6 V and

*R*= 470 kΩ. If

_{B}*V*= 0.61 V, calculate the base current

_{BE}*I*

_{B}12- In Fig. 43 the collector-to-earth voltage is 9 V, *R _{L}* = 3 kΩ and

*I*

*= 2 mA. Calculate the supply voltage*

_{c}*V*. If the emitter resistor is I kΩ calculate

_{cc}*V*.

_{E}13- In Fig. 43 *V** _{cc}* = 12 V, the collector-to-earth voltage is 6 V and the power dissipated in

*R*. is 6 mW. Calculate (

_{L}*a*)

*R*and (

_{L}*b*)

*I*

*.*

_{c}14- In Fig. 43 *R _{3}* = 1.2 kΩ and

*I*= 1.8 mA. If

_{C}*h*= 100 and

_{FE}*V*= 0.62 V calculate (a)

_{BE}*I*and (

_{B}*b*) the voltage across

*R*.

_{2}15- The transistor used in the circuit of Fig. 44 has *V _{BE}* = 0.63 V and

*h*= 85. Calculate

_{FE}*I*.

_{C}16- In Fig. 43 *V** _{cc}* = 12 V and

*I*

*= 2 mA. If 1/10 th of the supply voltage appears across*

_{e}*R*calculate

_{3}*R*. If

_{3}*V*=

_{CE}*V*

*/2 calculate*

_{cc}*R*.If

_{L}*h*= 100

_{FE}calculate *I _{B}* If

*I*

_{R}_{l}= 10/

*I*calculate

_{B}*R*

_{1}and

*R*

_{2}

*V*= 0.65 V.

_{BE}For the circuit of 6.16. calculate the d.c. input power. Also find the collector dissipation for zero signal conditions.

18- A transistor has *h _{FE}* = 120 and

*I*= 20 nA. Calculate its collector current when the base current is 20μA.

_{CBO}19- In the circuit of Fig. 43 *V _{CC}* = 12 V,

*R*

_{1}= 33 KΩ,

*R*

_{2}= 10 kΩ and

*R*

_{3}= 1.2 kΩ. If

*I*= 1.75 mA calculate the

_{c}*V*bias voltage of the transistor.

_{BE}20- The bias circuit of Fig. 20 is designed with the h_{f}£ value assumed to be the nominal value of 100. One circuit is constructed using this type of transistor where the *h _{FE}* value is the minimum of 70. Explain how the circuit operates to ensure that the collector current is very nearly equal to the designed-for value.

21- The signal voltage applied to the base of a transistor with g_{m} = 40 mS has a peak value of 0.1 V. Calculate the peak value of the a.c. component of the collector current. If the collector load resistance is 4.7 kΩ determine the output voltage of the circuit and the voltage gain.

22- An audio-frequency amplifier uses a FET with *r _{ds}* = 10 kΩ and g

*= 5 mS.*

_{m}What value of drain load resistor is needed to give a voltage gain of 40 ?

23- On the output characteristics given in Fig. 45 draw the load line for a d.c. load of 400 ohms. The operating point is *I _{B}* = 150 μA and the supply voltage is 20 V. If the emitter resistance is 100 ohms calculate

*V*,

_{E}*V*and the collector-to-earth voltage. Determine the peak-to-peak output voltage when a sinusoidal voltage varies the base current by ± 50μA.

_{CE}24- Fig. 46 shows the collector current of a transistor plotted against collectoremitter voltage for various values of base-emitter voltage. The transistor is used in an amplifier (Fig. 43) with *V** _{cc}* = 20 V,

*R*= 3.5 kΩ and R3 = 500 Ω . Draw the load line and choose a suitable operating point to give the maximum possible output voltage. Determine the peak-to-peak collector current when the peak base voltage change is 25 mV. Calculate the voltage gain of the circuit (

_{L}*a*) from the load line. and (

*b*) using the expression

*A*

*= g*

_{v}*.*

_{m}R_{L}25- Figs 47(a) and (*b*) show. respectively. the input and output characteristics of a transistor. The transistor is used in a single-stage amplifier with *Vcc* = 6 V, *R _{L}* = 1800 ohms and emitter resistance is 200 ohms. Draw the load line and mark the operating point for a base bias current of 20 μA. Determine the required bias voltage

*V*Calculate the ratio

_{BE}*δI*

_{C}/δV_{BE}26- Fig. 48 shows both the mutual and drain characteristics of an n-channel JFET. If *V _{DD}* = 20 V draw the load line for

*R*= 2000 ohms on the drain characteristic and select the operating point

_{L}*V*= - 2 V. A signal voltage varies

_{GS}*V*between the limits - 1 V and - 3 V. Determine from both sets of characteristics the mutual conductance of the device. Calculate the voltage gain (

_{GS}*a*) from the load line and (

*b*) using the expression

*A*= g

_{v}

_{m}R_{L}27- Fig. 49 shows a transistor output characteristic with a load line drawn on it. Determine the load to which this relates. Caculate the maximum peak-to-peak output voltage and current if the operating point is (*a*) *I _{B}* = 1 mA. (

*b*) I, = 3 mA and (

*c*) I, = 5 mA. Comment on the results.

28- For Fig. 49 calculate the d.c. power taken from the supply and the collector dissipation under no-signal conditions. Assume the base-bias current *I _{B}* to be 3 mA.