Integrated Circuit Design: CMOS Inverters , CMOS Gates , Bipolar Gates , Medium-Scale Integrated Circuits,LSI and VLSI Circuit Design,Multiphase Clocking,Increasing Packing Density and Reducing Power Dissipation in MOS Circuits,Gate Arrays,Standard Cells,Programmable Logic Devices,Programmable Logic Array,Reducing Propagation Delays,Resistance-Capacitance (RC) Delay Lines, Superbuffers ,Output Buffers
CMOS Inverters As shown in Fig. 6.9(a), the CMOS inverter consists of an enhancement NMOS as the driving transistor, and a complementary enhancement PMOS load transistor. The driving transistor is off when V in is low, and the load transistor is off when V in is high. Thus, one of the two series transistors is always off (equivalently, drain current and power dissipation are zero) except during switching, when both transistors are momentarily on. The resulting low-power dissipation is an important CMOS advantage and makes it an attractive alternative in VLSI design. NMOS circuits are ratioed in the sense that the pull up never turns off, and V O L is determined by the inverter ratio. CMOS is ratioless in this sense, since V O L is always the negative rail. If one desires equal sourcing and sinking currents, however, the pull-up device must be wider than the pull-down device by the ratio of the electron-to-hole mobilities, typically about 2.5 to 1. This also gives a symmetrical vo...
