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Showing posts with the label Testing of Integrated Circuits

Testing of Integrated Circuits:Introduction ,Defect Types ,Traditional Faults and Fault Models, Concepts of Test ,Types of Test , Test Methods , External Stored Response,Testing , BIST , Scan , IDDQ, Test Tradeoffs and Tradeoffs of Volume and Testability

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Introduction The goal of the test process for integrated circuits is to separate good devices from bad devices, and to test good devices as good. Bad devices tested as bad become yield loss, but they also represent opportunity for cost reduction as we reduce number of defects in the process. When good devices are tested as bad, overkill occurs and this directly impacts cost and profits. Finally, bad devices tested as good signal a quality problem, usually represented as defects per million (DPM) devices delivered. Unfortunately, the test environment is not the same as the operating environment. The test process may reject good devices and may accept defective devices as good. Here lies one of the basic problems of today’s test methods, and it must be understood and addressed as we look at how to generate and test integrated circuits. Figure 14.1 shows this miscorrelation of test to use. Bad devices are removed from good devices through a series of test techniques that enable th...